The Role of Graphene in Semiconductor Technologies



nano online simulation and more for nanotechnology okay good afternoon everyone so thank you for coming out on the last day of winter I'm sure so I want to welcome we're very fortunate to have shaloo Rocca G visiting us from MIT so I've gotten to know dr. Rocca G through the needs program so we've been interacting closely on a number of different projects she did her her bachelor's degree in the iit kanpur above even india grew up in a small town maybe even smaller than Lafayette yeah that's pretty small okay and then did her master's and her PhD at Georgia Tech so working on alternative switching technology focusing on interconnects for both electronic devices and spintronic devices and for about a year I guess she's been at MIT as a postdoctoral student working with Demetri and tinnitus on a variety of different problems including novel transistors but she's also and continues to be involved in work on graphene then and spintronics and other topics so it's the graphene work that she's going to be telling us about today welcome to Purdue or looking forward to your talk thank you mark for such a kind introduction and I'm really happy to be here some of the people that I have actually looked up to all my life as a PhD student are here and I feel extremely fortunate to be here and welcome to my talk on the role of graphene in semiconductor technologies before I get started I'll tell you a real story of how I got involved in graphene when I first joined grad school I started working an electric thermal modeling of carbon nanotubes and then graphene was a fairly new material at the time and people were still discovering his exotic physical properties and we were struggling a lot at the time with the interconnect problem not that the problem is solved now but I started looking at the potential of graphene for interconnect applications and the more I worked in graphene the more I realized that it had the potential for a lot of different kinds of applications but one of the things that people don't realize is that graphene technology actually opened doors to a lot of novel turing technologies that can be put to use in future for future applications so in this particular talk i'll try to tell you the things that I have worked in graphene and the projects that I am really interested in going forward so graphene is an atomically thin layer of carbon atoms arranged in a honeycomb lattice and it has applications in electronics like on chip interconnects and even RF circuits and it can also be used for flexible electronics like solar cells touchscreens sensors and integrating graphene with silicon photonics is a very important research direction and you can build active devices like photo detectors and optical modulators and even for health purposes you can actually attach a lot of chemical molecules and graphene and make it more or less soluble and guide it towards a specific therapeutic target so graphene as you see has a lot of different kinds of applications and in this talk I will focus on electronics which is on Shapiro connects and radio frequency circuits so I've partition my talk into three distinct components in the first part I'll motivate you as to why graphene makes sense for interconnect applications and towards this end I'll go over electron mobility in graphene I'll be giving you a specific example of multi layer graphene interconnects and I'll be showing you some of the advantages limits and opportunities of graphene interconnects as compared to copper interconnects at advanced technology nodes in the second part of my talk I'll go over a specific model that we call the virtual source model that I've developed for radio frequency circuits it's a static transport model that is also supplemented by a dynamic charge partitioning model we've done a lot of exhaustive experimental calibration with data from MIT Columbia University and also from IBM in this talk I'll be focusing on the new data that we got from IBM and then I'm gonna bridge gaps between the virtual source model and the model that Mark proposed based on reflection and transmission coefficients and try to extract some meaningful parameters for this technology such as mean free path effective mobility and ballistic velocity the end to demonstrate the model capability for circuit and system level analysis I'll be showing you Specter simulations of frequency W circuits with graphene devices and some of the topics that I'm interested in the future are related to graphene solar cells and integration of graphene with silicon photonics photo detectors and modulators so before I get started I want to spend exactly once life explain to you what the interconnect problem is so microprocessor technology has benefited a lot from dimensional scaling along Moore's law Moore's law is the law of economics not a law of physics like the Newton's law it tells us that if you shrunk your devices by X percentage every couple of years on the microprocessor you would increase binary information throughput and make more money for the industry very good and in fact that has been the mantra behind dimensional scaling for a number of decades which increased the transistor performance but sadly degraded the interconnect performance interconnects are these metal wires typically implemented in copper in a microprocessor that communicate information between point A to point B on the chip so let's say you were trying to do some computation and you wanted to transmit information from location to location B and if you couldn't do that in an energy efficient and a fast way then that would pose a bottleneck for this technology and at the same time you see that in a microprocessor more than 50 percent power is being consumed in the interconnect so the idea is that interconnects do place latency and power demands on the microprocessor and I have no idea why this is automatically getting switched so let me just do something here okay so interconnects to place latency and power demands in the microprocessor technology and graphene can actually play a role over there because of several of its advantages like high electron mobility low per unit length resistance lower capacitance it has a very good current carrying capacity and it can be integrated within existing semiconductor technologies here is a plot that shows per unit length capacitance versus technology over both copper and graphene nanoribbons that I acronym as G n R so every time I use G n R it stands for graphene nanoribbons you can see that the per unit length capacitance of graphene nanoribbons is much less than that of copper and therefore you can implement low-power interconnects with graphene ribbons but the question is that to be able to quantify the performance limits of this particular novel technology you have to understand the graphene material both its intrinsic and extrinsic properties I'll get started with the intrinsic properties of electrons in graphene so the intrinsic limits are imposed by scattering to do phonons both acoustic and optical phonons in graphene and here is a plot that shows the mean free path was a scheduled concentration in graphene and at reasonable carrier concentrations you can see that the mean free path can be as high as 1600 nanometers and in fact this was the mean free path that bulletin actually measured in his graphene devices but those devices were actually suspended between two contacts and there was no substrate on them right so such high mean free paths can be obtained but for real circuits you have to deposit graphene on a substrate and you also have to pattern it into narrow ribbons for real circuit applications and both of them will lead to an interaction of electrons with edges with the phonons in the substrate and with the charged impurities and will lead to a degradation in the mean free path and the mobility of electrons and those are some of the realistic effects that we need to incorporate in order to assess where graphene lies in this whole landscape of interconnect applications here is an SDS measurement of graphene on sio2 and you can see that it's very rough and if there are formation of electron hole puddles that also caused the smearing of the Dirac point and the the top picture is the term image of edge States in graphene which was done by UC Berkeley in 2011 and that states have different energy states and they lead to a lot of degradation in mobility so in our models for electron mobility we have incorporated all of those realistic effects but instead of getting into complex mathematical equations what I'll do is I'll try to present the final results and tell you some of the implications that it can have for interconnects so this plot over here is mobility of graphene on various substrates the different traces on this plot corresponds to graphene being deposited on different of substrates so I'm gonna focus on the topmost trace over here that is the light blue color if you can tell and the mean free path over there is about 300 nanometers and that is hexagonal boron nitride and graphene on boron nitride has the highest mean free path highest mobility because graphene because boron nitride is an isomorphous graphene and what I mean by that it has lattice matched and therefore it leads to less degradation but still 300 nanometers of mean free path is about 1/5 of what you could get if graphene was suspended between contacts so we see that these are some of the serious limitations of substrate interaction with graphene that needs to be included we have good match with experimental data as well for our models as you can see by some of the symbols that I've put on this plot next what I wanted to do was understand how the patterned graphene edges would affect the mobility of electrons in graphene so when you patterned graphene into narrow ribbons it makes the edges rough and that causes diffusive scattering of electrons at the edges which is modeled through an edge scattering coefficient called PG ni which lies between 0 & 1 0 is the perfect case of smooth edges and for diffusive edges PG NR assumes the value of unity so this is a plot that shows mobility versus width in a GN r or a graphene nanoribbon don't worry it's a very busy plot but I'll walk through all of the different sets of traces over here if you look at the topmost two traces that correspond to graphene being deposited on an extremely good substrate that does not introduce any additional scattering effects and also there are no edge scattering effects and you can clearly see that the mobility is in excess of 10,000 centimeter square per volt second which is very good the next to a set of traces which are these blue traces they correspond to graphene being deposited on a real substrate like boron nitride and you can now see that the mobility is are limited to only few thousands of centimeter square per volt second finally when you open the edges when you make edge roughness when you include the effects of edge softness you see the sort of a roll-off of mobility with the width of the ribbon and that can have serious implications for interconnect applications and you see that for connect with witches less than that nanometer the mobility would be limited to only few hundred centimeter square per volt second an important parameter that we have to consider for interconnect applications is their sheet resistance or the per unit length resistance because that determines the delay of the interconnect or the latency which is an important factor for us so a degradation and mobility would definitely lead to a degradation in that sheet resistance or the per unit length resistance that we are talking about and that I will talk about in the next slide so this is an N layer graphene interconnect I call it the multi-layer graphene nanoribbon m LG n R and it's between two contacts and it's deposited on the substrate the in-plane resistances are layer the perpendicular resistances R perp now our perp which is the perpendicular resistance in the structure is much higher than the R layer if we zoom in on this image a little bit what we see is when electrons are trying to come in from the contact into the interconnect there is a mode bottleneck because of the mismatch in dimensionality between the contact and the interconnect contact is a three dimensional material and the interconnect in graphene over here is two-dimensional and not only that the electrons only want to flow in the topmost layer why because current wants to take the path of least resistance and as I just mentioned the perpendicular resistance is very high and therefore the electrons don't want to penetrate into the deeper layers so what we really expect is that the distribution of the current would be non uniform in this vertical interconnect structure now most of the experiments that are done in multi layer graphene interconnects with top contacts naively assume that these contacts are coupling it equal to all of these perpendicular layers and that actually overestimates their performance so what we realized was that these bottleneck issues this non uniformity of current distribution is an important effect for interconnect applications that we need to incorporate in our models so here is a simulation MATLAB simulation of the distribution of current in a multi-layer graphene interconnect we considered to interconnect lengths the dashed one over here is five micrometers and the solid line is 10 micrometers what you see over here is that shorter the interconnect the more non uniform the current distribution is and that is sort of you know you can explain that by saying that for shorter interconnects the in-plane resistance is much lower so the current now really wants to flow in the top layer and it doesn't really want to go into bottom layer and this the take-home message is that the performance evaluation of these interconnects must incorporate imperfect coupling of contacts and graphene the top was circuit over there is the schematic of the driver interconnect receiver that we are using for evaluating the performance of these interconnects and the bottom circuit shows the equivalent circuit corresponding to that where the interconnect is represented by a distributed RC Network which is over here this this one and the points that I've labeled as C 1 and C 2 these are the contacts between the driver and the interconnect and they do take into account mode bottleneck issues the delay is given by the expression over here there are 3 distinct components and the expression 1 is the first part over there is independent of the interconnect length that is the length through which you are trying to communicate information it is mostly limited by the source or the driver resistance and then we have a part that varies linearly with interconnect length and the third part is independent of the interconnect length for short local interconnects it's the first two components that matter a lot the third component is not that important and it's the short local interconnects that we are trying to target over here instead of the long back into the line like the topmost layer we're not targeting that and the energy dissipation is simply given as the amount of energy that would be needed to charge or discharge the total capacitance at the output node so let's look at what happens to the delay versus the technology here this plot has both copper and graphene delay with side contacts and top contacts the interconnect claim that I'm targeting over here is ten gates pitches one gate which is the average footprint of a two input NAND gate on the microprocessor so this is very interesting when you see it site contacts this is what people predicted ok graphene is really good it has great sheet resistance and therefore it will perform better than copper which is what site contacts the red line shows the black one is the copper but if you have these top contacts where the current is really not coupling to all of the perpendicular layers you will see that graphene starts to behave worse than copper at Advanced Technology nodes so the key message over here is that size effects and improper contact couplings will tend to hurt multi-layer graphene interconnects quite a lot at Advanced Technology nose and this needs to be incorporated in all of the technology assessments that we do with these interconnects the next plot over here is the energy delay product versus technology year and we see that both side contacts and top contacts perform better than copper interconnects and the reason for that is copper the the graphene interconnects really have lower capacitance and therefore they can beat copper in terms of energy delay product or even in terms of energy right still you can see that top contacts are not as good as side contacts so that was the whole point of assessing the advantages limits and opportunities of these interconnects by taking realistic effects into account so to summarize part one I very briefly showed you that graphene does have the potential fall on chip interconnect applications particularly short local interconnects but at the same time you have to take into account substrate coupling you have to take into account the effects of edge roughness and you know mode bottleneck imperfect coupling and then only you can assess the real advantages limits and opportunities of any technology so this was just to motivate you to the fact that any kind of real circuit applications when you are target and you really have to understand what is going on at the fundamental physical level so next I'll move on to graphene yeah sure sure well that is when resistance times capacitance for the interconnect is valid only for very long interconnects where the source resistance does not play a role but for short local interconnects if you are using these advanced transistors really have very high resistances so those need to be taken into account the delay has three components one is independent of length the other is linearly with less and the third one is quadratically with length so what we are targeting is the first two components where it's either of length or linearly dependent or interconnect length so over here it depends actually I really see your point but over here what we're doing is with the pure assume that the graphene is deposited on a very good substrate like boron nitrite that has a very high mean free path of 300 nanometer and even the more bottleneck issues that I'm talking about contacts we're assuming a transmission coefficient of about 30% so you can see and and that it's sort of you know an optimistic way of looking at it but if I not at this optimistic way of looking at it we see that graphene does not do a very important stone so if you were to take graphene on SiO 2 for instance it would be much worse or if the edge roughness was more it would go even even like it would be have a much higher latency than copper so these are like optimistic yet we have incorporated some of the realistic effects that matter to us I I'm sorry I don't remember the values off of my head right now but I can show them I can discuss that with you later but it's kind of very very high I'm not an experimentalist but graphene can be done through CVD or exfoliation as well yeah yeah so what we're doing in these calculations is we looked at a couple of different substrates as I showed you earlier we have all of these different substrates but the plots that I showed you for delay were only for graphene on boron nitride and like I said if you did analysis with more experimental data you would actually end up getting much worse performance results for graphene and sometimes you want to show people good and the bad with a mixture so this is what I my point is that there are Bad's and there are quotes as well so get all the questions about interconnects all over here before you buy the transistors so help me so I think conclusion is graphene could be better than copper fire energy and it's if I understand correctly it's not because of sheet resistance it's because of capacitance is that right yes it's very thin so what we're doing for graphene capacitance in these devices when I published these results we did not include quantum capacitance effects into account we had only electrostatic effects but we now have a full simulation that takes into account the capacitance between the layers quantum capacitance and all those effects but the conclusions are pretty much unchanged that it has a lower capacity about 50% power dissipation was due to the interconnects about 25% with two gates the charging discharging and then the rest of the parasitics it's press it eclipsed it's when Intel people did this they call it diffusion so I didn't want to change it and I think they're talking about parasitics because now for advanced technology nodes the parasitics are almost equally high as your actual gate capacitance they are becoming very very important so I think that is what they're talking about but that is all related to the gates that was the point the point is that for RC or for delay performance graphene does not really compare very well against copper interconnects and we were targeting very short local interconnects and even for short local interconnects the conclusion remain pretty much unchanged so for capacitance yes so we tried building I mean in spice not an actual circuit sub-threshold circuits with both carbon nanotubes and graphene because they have low capacitance and they could actually beat the traditional it's not a semiconductor it's a semi metal yeah yeah yeah yeah yeah you have a little bit of a bandgap yeah well as for graph for interconnect applications unfortunately you have to patent graphene into nano ribbons so that unintentionally opens up the bandgap and people have argued that zigzag versus aren't shared one of them would be metallic and the other would be semiconducting and I beg to differ because none of the experiments have shown metallic characteristics so that is also one of the limitations why for transistor applications you want a band gap for interconnect applications you don't want a band gap so yeah it's sort of limiting but the motivation came from the fact that in many ways graphene was similar to carbon nanotubes when we when we started exploring the potential of carbon materials for interconnects we wanted to see how graphene could help us alright so not all research results lead to positive results I think that finding the you know limitations of a technology is also very important to guide the Rees experimental research in the right direction yes we have so this meant the plot that you are showing us I showed you over here was computed for an ideal optimal number of layers for DNA performance and the thing is that as you keep on increasing more layers the performance benefits don't scale with the number of layers oh we did all of that analysis and I don't know the paper very well so I think yeah for those ideal ones also they have these limitations that's what I said that yeah yeah for ideal ones also a lot of limitations all right so I shift gears and move on to graphene for analog RF circuits this is the work that I did last year at MIT so for RF this is a graphene with two gates graphing transistor with two gates you have a top gate and a bad kid and it's back oxide which is typically sio2 and it can be done through CBD or exfoliation the typical transfer curve of a graphene field effect transistor looks something like that and it has a minimum conduction point which we call the Dirac point and to the left of this dialogue point we have the hole current and to the right of the Dirac point we have the electron current and this is an amp a polar transfer characteristic and it's very interesting this novelty of graphene does not exist for silicon transistors which are unipolar transistors and we can use this for building frequency W circuits with a single device something that is not possible with silicon transistors another feature that emerges from this particular plot is that you see that the electron in the whole branch currents are asymmetric and this asymmetry arises typically because of the way these source and drain contacts coupled to the electrons and holes in the graphene layer the couple very very differently so if I want to simulate a frequency W circuit the first point over here would be you know coming from our circuits background people would say okay where is the model file give me the model file so we need to develop a compact model to explain the transfer car at the transistor characteristics and I think there are three essential features that any compact model should have the first one is that it should capture the essential physics at the nano scale transport and it must be a compact analytical description we don't want to run numerical analysis and the third one is that it must be true to experiments so the model that we have developed for graphene field effect transistors which we call the virtual source model accomplishes all of this and more it's a quasi ballistic transport model that goes all the way from drip diffusion to ballistic regimes of transport it is ambipolar and it also comprehends the asymmetry that is introduced due to electron and different electron and holes channel access resistances and finally we have supplemented the model with a self-consistent channel charge model but before I get started I'll take one slide when asked I'll take one slide explain to you the physics of the virtual source model the top picture over here is a field effect transistor with all of its terminal voltages label and the bottom picture is the profile of the conduction band as a function of position within the channel and the point labeled as X naught is called the top of the bag or as we commonly called the virtual source point and vxo denotes the velocity of carriers at the virtual source point the current and saturation is simply given as the product of the charges at the virtual source point and the velocity of these charges at the virtual source point then we multiply this with an empirical function f Sat to achieve transition from saturation to linear regimes of transport yes that is mathematically implemented in a way that it goes to unity when the transistor is in saturation but I won't have time to get into the implementation of F sac but I still want to point out that F Sat depends on the drain to source bias it depends on mobility the gate length the injection velocity and there is this parameter beta which actually can be obtained upon calibration with experiments so that is an empirical parameter how is this model applicable in graphene graphene is very unique because it is capitalist material and therefore there exists two virtual source points at opposite ends of the channel the picture on the right shows the electrostatic potential profile in the graphene channel the points labeled in blue is the virtual source point for electrons and the points labeled in red is the virtual source point for holes note that even though I've called both of these points as X naught these existed opposite ends of the channel and because of the perfect symmetry between the conduction and valence bands in graphene the virtual force injection velocity is for both electrons and holes are identical and we call them VX o so the current is simply given as the superposition of the electron and the whole branch currents and again we have the function f Sat over there to achieve this transition from saturation to linear regimes of transport so if we have Q X so and QX o H as functions of the terminal voltages we'd pretty much be done with our compact model so how do we come up with compact models for Q X so and QX o H we were basically inspired by silicon material for the bandgap so the expressions that we word opted are typically valid in materials with the bandgap the advantage of these expressions is that the model can very naturally be extended to bilayer graphene where a band gap can be opened and expressions are given over there I'll point out a few essential features in these expressions Q disks that you see you over there on the right side the disorder induced charges which basically exists in graphing because of these electron hole puzzles and VTN and VTP these are the threshold voltages corresponding to the electron and the hole branches of current and we have a few fitting parameters over here the first fitting parameter that causes in these expressions is n which is related to the sub threshold slope of these devices and then we have a fitting parameter alpha which basically governs the shift in the threshold voltage from sub threshold to strong inversion operation regimes and we also have Delta V over here this one that basically approximates the effect of traps charging interface trap charging and we have FFP and ffh which are for me like functions so question that you would ask me is how do you know that these expressions are valid in graphene and to answer this question we did numerical computation of charges by exploiting the concept of voltage divider networks at both the virtual sources for electrons and holes in a quasi ballistic transistor the concept of virtual source this voltage divider network is indeed valid at the virtual source points even though it may not be valid within the rest of the transistor and the voltage divider network by electrons is here and CG is the oxide capacitance CTO is the quantum capacitance which depends upon the surface potential and likewise we have a similar structure for the holes and there the quantum capacitance depends upon the surface potential at the drain end so what we did was we used fermi-dirac integrals and voltage divider networks to compute the charges numerically another thing that goes into this computation is the density of states and we have to use an appropriate density of states for these calculations what I mean by appropriate density of states is our density of states with a broadening function that can actually simulate the effect of electron hole puzzles in graphene and then you could compute your charges numerically I'll show you some comparison results of charges that were obtained using numerical and our compact modeling approach so that shows the net charges in the channel at the virtual source point versus the gate voltage we have for traces over there the four traces correspond to two different values of the equivalent oxide thickness for the gate and two different values of the broadening for energy for a density of states so sigma over there is the broadening in the density of states the symbols have been obtained using the numerical model and the lines have been obtained using the compact models they actually it looks very good so in the compact model we've adjusted Q disk which is the disorder related charges and we've also made some slight adjustments in the equivalent oxide thickness in the compact model to come to this and we have fixed n equal to 2 and alpha equal to 6 for this particular plot over here next I'll show you the adjustments that we have done in Q disks which is the disorder charges and the equivalent oxide thickness to come to this result so Q dis which is the disorder related charges versus the broadening in the density of states so we see that if you look at the dashed line that is for an equivalent oxide thickness of 50 nanometer and we see that the disorder related charges were fixed between 1 to 3 times 10 to the power 11 per centimeter Square and the eot was adjusted within plus minus 10% of its physical value so we have sufficient confidence in in our compact models that we are using four charges and we did actually a very comprehensive ly square curve fitting analysis to come come to this particular result so I I think it's um it gives us a lot of confidence in what we are doing so asymmetry in current conduction is another important aspect of graphene transistors and this is a typical transfer curve of epitaxial graphene for a 3.5 micron long transistor and we see that for the same shift about the Dirac point the electron branch current is more than the hole branch current and we know that the mobility of carriers and these devices should be roughly same that means the intrinsic mobility should be the same and also the virtual source injection velocity of the carriers should be the same because of the symmetry between the conduction and valence bands so how does this asymmetry really arise it arises because of the difference in the channel access resistance for electron and hole branches so the top picture over there is the field effect the graphene field effect transistor now connected to its source and drain resistances both RS and Rd are different for electrons and holes and in our model we have indeed included two different resistances called our Alec and our hole which can be obtained upon calibration with the experimental data so I'll show you a phenomenological circuit model to capture this asymmetry RS is implemented by this bottom circuit block shown over here and Rd is implemented by the top circuit block shown over there and both of them are exactly symmetric you can see from this that I hold which is the whole branch current is affected only by our hole which is the whole channel access resistance and likewise I elec is affected only by our elec and also you should note from this particular implementation that this now makes RS and RD nonlinear voltage dependent resistances and here is our simulation result for the transfer characteristic of a particular graphene field effect transistor here I've fixed the our electro 500 ohm microns and our hole was changed when our hole has changed you can clearly see that the current in the hole branch and the current in the am bipolar region this is the ambipolar region around this this point over here only those regions are affected why because holes play a significant role only in those regions in the electrons side its electrons that are carrying the current the majority of the current most of the current so that part is really not affected so with this slide I'll conclude my findings are on the static transport model and I'll go on to the dynamic model what does the dynamic model mean dynamic model actually gives us the charges at the different terminals the source terminal the drain terminal and the gate terminal we are using the word that in charge partitioning scheme which is valid irrespective of whether the transport in the channel is drip diffusive or ballistic as long as quasi static transport conditions are maintained in the channel and Q s and Q T are given by the expression expressions shown over there and in those expressions we have q HX q e^x those are position dependent electron and hole charges in the channel and at low VDS you can still model your transport as drift diffusion with no velocity saturation which is what our acronym is dd and VSAT and then finally once we have the quasi ballistic charges we blend them with the drift diffusion charges using the same F Sat function that we've used for transport formulation so I won't actually get into how we've implemented these trip diffusive charges but I'll get into how we've implemented the quasi ballistic charges because that is important and that was the missing link in all of the previous modeling efforts that were being done in graphene field effect transistors so how do you compute the quasi ballistic charges vini was actually two conditions two physical conditions over here the first is the condition of current continue to pour both electron and hole branches which are given by the two expressions over here the left-hand side in these expressions is known to us because we have done the transport formulation the static transport formulation we don't know the right-hand side but if we can find the position dependent velocities which are vixx v HX X we can come up with the position dependent charges go back on the previous slide do our integrals and come up with all of the charges and to come up with position dependent velocities we are using the condition of energy balance and I won't get into the math but those are the two equations that give us position dependent velocities to me the most important parameter that goes over there is this that are over here that actually is the fraction of the PDS energy gained by carriers as they travel along the channel so if it was a perfectly ballistic transport data would attain its highest value of unity for any quasi ballistic transport that hour will lie between zero and one so I call it the ballista City parameter or a measure of the ballista City in the channel I'll show you some simulation results of charges versus the gate to source voltage for these devices this was done for a 210 nanometer device the drain to source voltage was fixed at one volt and you can clearly see that the charges changed their polarity as the transport changes from one carrier type to another carrier type and that's what I've been emphasizing the graphene is ambipolar it can have either electrons or holes depending on the voltage regime that you're trying to operate and the the parameter was fixed as 30% in these devices now the question is if you used or drift the fusion formulation what would happen to the charges this is what would happen the DTN VSAT charges would be overestimated so the drift diffusion needs more charges to generate the same amount of current and therefore it will lead to an overestimate estimation of all of your charges and that can have serious implications for your device performance because now charges are more capacitances will be higher right so once you have the charges as a function of voltages which is what I explained to you now you can come up with capacitances as functions of voltages using the expressions given over here I'll show you a typical example where we did the gate capacitance simulation versus the gate voltage and we have both the drip diffusion charges and the quasi ballistic charges the bunch over here are quasi ballistic and the top ones are the drift diffusion charges and that's what I've been emphasizing that the drift diffusion charges are always overestimated and therefore the capacitance is also overestimated and there's another interesting feature that emerges from this which doesn't really happen in silicon and that is the appearance of that hump in silicon you will never see capacitance doing something like that and over here you see something like this and that's only because current is being carried by both electrons and holes in graphene so if you actually bias your transistor somewhere over here or somewhere on the other side you would get a higher current gain right because knock current gain depends on capacitances if the capacitances are lowered you would end up getting a higher cutoff frequency higher current gain but as I'll talk about in one of the later slides for frequency W applications you have to bias your transistors at the minimum conduction point so that's a challenge so with this slide I conclude my findings on the dynamic model and I'm going to move on to experimental calibration alright so we do experimental verification with a lot of different kinds of devices for the iodine and paper that I did last year we use data from MIT and Columbia University over here I am showing you the data from IBM these are epitaxial devices show down on silicon carbide and they were very generous to give us state upper gate lengths ranging from 650 nanometer all the way to 40 nanometers now these are at the output curse of 650 and 300 nanometer devices and the symbols are the experimental data and solid lines have been obtained using our model we see that an extremely good match is obtained between the two and we were able to extract some of the parameters in the model in a physically meaningful and realistic way this is the data for one forty and forty nanometer channel length devices the second output data and we again see a very good match between the experiments and our model we've used an exhaustive numerical d square curve fitting analysis to extract all of our parameters and obviously one would always ask me how can you extract them because it's always introduction between the parameters in a model and that's a discussion probably for another time but we have significant confidence and the parameters that we are extracting using our numerical implementation so in this overall we had seven but having said that I did a lot of sensitivity analysis to remove certain parameters like I'm not optimizing better for instance I'm going to take the electron and whole branch resistances from measurements and things like that so we did like one by one so we started with just two basic parameters mobility and vxo and then we started optimizing more and more and started to see where we get that best point so seven is I think total well it depends once you fabricate it most of the time we interact with experimentalist to find out if the contact resistances have changed or the contact resistances have remained the same but for some of these devices you see a little bit variation in contact resistances so have an exhaustive table of extracted parameters which I can show you so the resistance is over here over somewhere around 500 ohms micron so yeah but they go all the way up to like thousand and fifteen hundreds I've seen a lot of variation yeah these are very contact limited devices for shorter channel lengths we have not been able to successfully see any saturation effects so another question that comes from this is how do you know what your injection velocity is for these devices so those are some very physical fundamental questions that we need to ask ourselves so we don't see any saturation that's true all right we also looked at the s-parameter measurements of all of these devices the plot over here shows current gain versus frequency for all of the different channel length devices that we got from IBM the different traces are 440 nanometer all the way up to 650 nanometer and the symbols are the experimental data and the solid lines are our model please note that in our dynamic model we are not introducing any additional fitting parameters all the parameters have been obtained from the static transport formulation and therefore our dynamic model is self consistent with the static model and the point where current gain becomes unity is the cutoff frequency so we've been able to estimate the cutoff frequency is very nicely for these devices and here we see if the cutoff frequency versus inverse of the gate length the symbols are the experimental data and the red solid line is from our model the quasi ballistic model so again I went back and tried to lose the trip diffusion formulation which people have used a lot in the past I saw that that model was not able to predict the cutoff frequency versus gate length behavior accurately and this is also a signature of the fact that the transport in these devices is indeed quasi ballistic also we've been able to extract the ballista City parameter that you can see in the inset of this second plot as a function of gate length you see that the ballistic city parameter changes from about 0.1 to 0.6 as the channel length changes from 650 nanometer to about 40 nanometer which is expected because the shorter the channel gets you expect it to be more and more ballistic we don't yet have a good understanding on how this ballista City parameter would change with the different mobilities and different which mean free paths of these devices which is again a question we are looking into alright so yeah this is current gain yes that's a very good question again so right now the output resistances are very very low for these devices and these are very contact limited devices so we assume we extract the vxo from the devices then we hope that it is what we are really expecting it is and that's a very open-ended question and I I don't have a good answer so if we don't know if we can use it for for logic or for those applications yeah yeah yeah so even for our not I understand your point of how do you define an R naught for these devices if you're not seeing saturation so R naught for us is directly related to VX o which is the injection velocity which happens in saturation if there is no saturation how did we define R naught so we extract the exo and from that we go back and say okay VX o is this this is what a hard knot would be and we hope that that is they are not well for now I don't know if any other good way to go and do this charge party people have talked about a lot of different kinds of charge partitioning schemes and this is one of the charge partitioning schemes that I'm presenting and maybe you can point me to with other kinds of charge partitioning schemes that to exist in literature so I I know that there are plenty of those and some that you know assign more weight to the source and you know all those kinds of things so March should answer that question so what my goal would be next is to study that potential profile and understand where the barrier is but for that we need a lot of quantum mechanical simulations and the NEEMO team at Port you should probably we should probably collaborate with them and that is exactly so what are we different what we're defining as the top of the barrier or the virtual source point we need to get a more physical understanding of it doing all these profiling of the energy bands and things like that which I hope I can work with people at Purdue and understand I've been talking with people and it's a big question for us to understand that right now yeah all right so the next thing that we wanted to do was we wanted to understand some physically meaningful parameters for this graphene technology that I have been analyzing and this is mean free path and effective mobility so the apparent mobility or the mobility that we extract from the huius model can be given by the Matheson's rule of a ballistic mobility and an effective mobility that is valid in a long channel device and the ballistic mobility varies with the gate length it's linearly proportional to the gate length as you can see over here and there is the mean free path of the device if you did a little bit of math you can show that this inverse of mobility which I'm getting from the VF model can be expressed by the equation given over here what am I trying to do here what I'm trying to do here is I'll plot 1 over mu versus 1 over LG and I hope to get a straight line and when I get that straight line the slope of that straight line can give me information on lambda over mu effective and 1 over mu effective that is what I'm trying to do and I'm trying to understand what is the effective mobility for this graphene technology that I have been analyzing and what is the mean free path that I have been analyzing all right so this is what I'll do this is a table of the mobility that we've extracted from the virtual source model and this is the gate length and I've plotted the inverse of the mobility versus inverse of the gate length the symbols are these extracted mobilities or the apparent mobility of this device and we see that they fall very nicely on the straight line so these are fitted and we have actually gone back to the experimentalists so what these people have done is they've measured they measure their mobility in like a big channel device so then what they measure is an effective mobility and sometimes people also do short channel mobility measurements but I do not have any confidence in the way they extract their mobility for a short channel device because there is this ballistic mobility effect which needs to be incorporated a lot of the time experimentalists fail to account for that so these they are included they all of them are included to extract these mobile varies so contacts sometimes they give us the values and sometimes they don't and it's a kind of question of how many parameters are you optimizing what are you optimizing are you getting the right results and things like that yeah yeah but four things I didn't get any data from IBM on the mobility of the devices so these are actually extracted from the virtual source model yeah yeah so we fitted that with a straight line and what we get is the effective mobility of about 2,700 centimeter square per volt second and a mean free path of about 175 nanometer for this particular technology next we wanted to look at the ballistic velocity of these devices so if we look at the saturation current from the we s model we have an expression for the saturation current and if you go back to Mark's model which actually dealt with the reflection transmission coefficients we have a model from that and if we combine both the models we can show that what we are extracting from the virtual source model can be related to the ballistic velocity by a simple expression given on the top right hand side the question is this lambda over here which is mean free path does it remain the same in saturation conditions and the linear transport regimes but we are assuming that it remains the same so what I'll do from here is we have extracted vxo from our vias model from the transport IV data then we plot 1 over v XO versus LG and that we hope to you know we hope that it falls in a straight line and the y-axis intercept gives us the inverse of the ballistic velocity so this is what we did we have the inverse of the velocity versus the gate length the table over here is the extracted parameters extracted vs velocity and the symbols over there are the same data that we extracted and we see that it falls in a straight line and we can come up with a ballistic velocity which is about 8.2 times 10 to the power 7 centimeters per second and this is very close to the Fermi velocity of the graphene electrons all right so we have tried to somehow bridge the links between the virtual source model and the reflection transmission coefficient models that model that existed before through through this exercise next I'll go on to simulation of graphene frequency doublers so this is a single-handed graphing frequency doubler and we have a Chifa that is biased to the Dirac point and we give it an input frequency of F and at the output we get the duck double the frequency and then that is a differential ended topology where we have two symmetric graphing field effect transistors and the difference between the differential and the single ended topologies is this that that has that suppresses the feed-forward of the fundamental component and it also suppresses furious components in your output so as a frequency table what I'm really hoping is to get double the frequency at the output but I don't want a triple triple frequency component or you know other higher order harmonics so that actually does a better job with that and not only that its amplitude of the fund or the double frequency is also high which I've tried to somehow show through you know a higher amplitude signal at the output so we implemented the very low gain model and we ran Specter simulations for the time domain analysis and periodic AC analysis and we see that defense topology performs better than single under topology in terms of the amplitude but that's not the take-home message over here what I want to drive over here is that our model is continuous currents charges and the derivatives and it is very suitable for using in analog circuit simulation and we get a higher output signal with differential frequency W that's always there I'm not I won't be able to show you the analysis with the periodic AC yeah yeah yeah so mismatch will actually make this go very bad it's much worse for single-ended topology because it doesn't have a matching you know transistor with it yet when it will make it it'll make it much worse so make it much worse yeah all right good so to summarize part two we've developed a static transport model that is valid in both uni and ham before the transport regimes we have captured the asymmetry in current conduction because of the different electron and hole branch channel axis resistances we've developed a dynamic model that is cells consistent with the static transport model it yields continuous charges and capacitances and it's valid from trip diffusion to ballistic transport regime and we've calibrated the model exhaustively with DC and s-parameter measurements of GFS we've been able to extract mean free path effective mobility and ballistic velocity we've also done some circuit simulations of g5 frequency doublers to demonstrate the model capability for circuit and system level analysis so going back to graphene what I personally think what I would like to do in graphene in the future and where I think that the whole field is really going I mean there are plenty of directions that one can take I'll talk about solar cells and photonics photo detectors and optical modulators so craft scene can be used in photovoltaics which basically deals with converting light energy into electrical energy and graphene has potential to be used in low-cost flexible solar cells because of its advantages like high transparency invisible mechanical strength and flexibility I think that there have been plenty of experiments particularly ones that are being done at MIT in Jenkins group that actually use graphene as the top electrode but I still feel that there is a lot of gap between modeling and simulation and experimental efforts in this particular technology and I think modeling would be able to address some of the unique challenges of this technology as to how graphene interacts with the substrate but the organic substrate in particular I have done work on interaction of graphene electrons with different kinds of inorganic substrates but it would be important to understand how it interacts with organic substrates how does it couple with contacts contacts have been a very daunting challenge for this technology and also have multi-layer varies as a multi-layer transmission coefficient varies with the number of layers that are something which we need to understand because as I've shown for the interconnect applications multi-layer has better resistance or lower resistance compared to single layer graphene which is important and that could also be very useful for solar cell technology and my aim is to guide the experimental research in this direct you know in the right direction also learn something from them so that we can finally highlight the major challenges limitations and opportunities of this very important technology the next thing is coupling of graphene and light I think integration of graphene photonics within a silicon photonics platform is a very important research direction and in this hybrid circuit the passive components such as light right routing and guiding can be implemented in sub micron silicon wave guides where has the active elements such as modulator and detectors can be implemented with graphene and also the analog circuitry can be implemented in graphene that drives these photo detectors and I think one of the reasons why I am proposing this is because graphene has a very strong light matter interaction in the mid and far infrared frequency range which has typically been considered as the frequency gap between electrical and optical systems and I think a graphene can be used for terahertz communication and spectroscopy made and file infrared imaging and all those all those things but there are plenty of challenges the first challenge that I think is on the physics and scalability side we don't really understand the intra and Inter band absorption in graphene very well we've been using the conventional route formula to analyze optical conductivity of various materials we don't know if that would be applicable in graphene that's the first question the second is how does graphene coupled with the plasma how do plasmas in graphene coupled with the substrate how does the effect of the ribbon width change the dispersion relationship of these plasmons that exist in graphene so those are some of the physics and scalability related questions and the second part if we really want to do this heterogeneous integration and build a hybrid circuit simulation capabilities are lacking that is one of the biggest challenges very low K has catered exclusively to electrical circuits community and we don't have a very good way of representing photonic quantities within their native nature's and disciplines and I think attacking the problem bottom-up would be a good idea where we can actually represent some of these photonic quantities in a very natural natural way and that would actually assist in the circuit and system design and finally this is my last slide and I think that craftiness assured us into this two dimensional nano electronics research era which would play a very important role going forward I think we need to understand the applications of 2d materials outside of logic could be flexible electronics or optoelectronics for instance there are plenty of challenges as I have experienced from my you know experience in interconnects and RF circuits there is a small density of states the coupling of 3d contacts to two-dimensional contacts top contacts versus side contacts Schottky barriers question off top of the barrier does that really exist things like that and then how to do dielectrics on 2d materials and gate control and finally I think that we need the development of new simulation capabilities that are specifically tailored for 2d materials and this should be very much coupled to the experiments so that we can understand we can leverage the experimental results and build our theoretical models better and also leverage some of the opportunities that exist here in terms of MIMO and things like that where we can understand what is truly going on and in this area and that would be a very interdisciplinary outreach I believe to you know hash arose into this differentiated and accelerated technology innovation of the future which is what Dennis buss calls it thank you very much for your time you could get it from you can't I don't think so you can do it you can buy us you're probably you can bias your device either in the electron branch and whole branch and try to accurately extract your source and drain resistances but I don't know York do you have like I think you have worked in extraction of contact resistances and things like that so do you think that experimentalists would be able to understand that there are differences in electrons and holes with different methods if use in topic back a back gate then in really shift the respective curves maybe the curve that comes from the contact gated region and from the middle gate region relative each other and can really disentangle those resistance contributions so I think in general there is a way to together be experimental and also think that mobility measurements are not being done accurately for short channel devices I think you probably you have a very nice paper in IDM that talks about how to do this accurately for short channel devices by removing the effects of this ballistic mobility and things like that yeah so do you think that this parameter you kind of alluded to you this see the ground there is something that's like fairly well reproducible across like a broad range of samples or is it like just like kind of like each experimental procedure is going to produce it start twisting see that because I think at least you seem to be assuming about Zita was was uniform across like I said it devices with different channel names now as it actually scales with channel length so the shorter you make your channel length at all becomes higher because there is ballista City and the shorter you so you have to compare your channel length with the mean free path for that technology Oh dad I was just doing for one simulation I just wanted to show you one particular simulation of what a quasi ballistic charge model would do and what a drip diffusive charge Mortal would do and that was only for one channel length device so Sarah we are actually extracting from only the s-parameter measurements so that is the only factor that we get from this measurement by rest of the transport parameters or rest of the parameters that go into the dynamic model come from the transport formulation so this is the only one that we extract from this so if we didn't have that we would not be able to reproduce this very nice fitting that we see over here so that ballista City that you see that varies from very low to very high and it has to be between 0 and 1 now the big question is how does it scale with the mean free path or will filters be generic will this be reproducible I don't have answers to those questions and I would hope that it is reproducible and that we always see it as it also depends on how people are doing their measurements for this s-parameters because the moment you change your bias voltage as you can shift from electron branch to whole branch and then even though you would want to see that behavior you will not see that behavior and in fact I was talking with IBM and they did their measurements on the whole branch for this and hold branch for these devices has higher resistance than electron branch and they didn't do their measurements on electron branch and it feels very strange to me because IBM always wants to publish the highest cutoff frequencies and I went back to them and I said you know my model shows that your electron branch should have had higher cutoff frequency why did you not do that produce that in your nature paper and I said oh we didn't realize because what really happens in these devices has cut off frequency increases as you start coming close to ambipolar transport it decreases in ambipolar and once you go to electron it again starts increasing so once they started seeing those decrease in cut-off frequency they stopped doing the measurements thinking that it would be a uniform trend and it would exist forever so they didn't understand them the the issue of modeling behind it and I go back to them and ask then can you go back and do the measurements on electron branch so I have to push them very hard to do it but hopefully maybe they will in future I don't know yeah it would be the best test for the model because that's what my model tells me that the and the polar part has very high capacitance so you are expected to pour down in frequency but then again you will pick up pick up in frequency they didn't they didn't cross them beep yeah they do but in this case we didn't have GM measurements now what really happens in these devices is that the contacts tend to dope graphene underneath the channel so most of the times contacts will dope it either n-type or p-type so that when you actually go from in the channel if the carriers change from n to P type is an NP Junction or a PN Junction that gets formed and that is different for electrons and that is different for holes if it's a PN Junction obviously you know it's not a good thing if it's a P P Junction it's a good thing or an N n Junction it's a good thing the potential barrier height at the contact if you have to understand that very clearly you have to see how the potential profile changes underneath the contact and how it keeps changing in in the so that change is different for electrons and holes okay so I'm gonna jump in as my role that seminar chair and that's for one more question because we have a packed agenda and I think that does this is a very good question and I think that in these devices it gets limited and it's a very it's a very involved philosophical question right now for me and I think that contacts tend to play a bigger and bigger role as channeling gets shorter and shorter so yeah yeah yeah yeah yeah but still the if the contact resistance is not scaling at all with channel length and you make a channel shorter and shorter the overall device tends to get limited by what the contacts are really doing so contacts are not becoming anyway better with technology a length scaling in this particular case and then again the question is if graphene does not have a band gap then why does it even saturate for longer channel devices a very good question I think probably we'll have to go back and check how the and these keep changing with the the on/off ratio because we're really not targeting one of issues over here we are we really because these have like very poor on of maybe like three or four something yeah yeah yeah yeah yeah yeah yeah so yeah okay so thank you very much

4 Comments

  1. Ritwik Barman said:

    Really ..kanpur is a pretty small City ?? Btw your presentation is really a big tatty ..big big dislikes from your India ..

    June 30, 2019
    Reply
  2. Karthikeyan Mitran said:

    Its good to see someone with this good understanding for the semiconductors. My summary of the video for the impatient, In short we have a 7 parameter Graphene based transistor model, but was able to hold true with experimental results, though the switching characteristics might be not that good it seems to do good with analog circuitry, and makes magic with the frequency doubler. Thanks for the video

    June 30, 2019
    Reply
  3. Soumya Ranjan Panda said:

    Indians All over.. Nice…

    June 30, 2019
    Reply
  4. Jaykumar Vaidya said:

    great

    June 30, 2019
    Reply

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